1. Field of the Invention
The present invention relates to a semiconductor integrated memory manufacturing method and device, more particularly, a semiconductor integrated memory device, and more particularly, to manufacturing method in which a capacitor is formed prior to formation of a transistor on a single substrate.
2. Discussion of the Background
The semiconductor integrated ferroelectric memory device has a non-volatile characteristic such that the device does not lose its stored information even after power source suspension, and is supposed to be introduced into practical use. The device is expected to obtain reading and writing performance as fast as the conventional Dynamic Random Access Memory (DRAM), as has been recently demonstrated when the film thickness of the memory cell capacitor is thin enough such that spontaneous polarization of the capacitor quickly turns around. Also, the memory cell consisting of one transistor and one ferroelectric capacitor can store 1 bit; therefore the semiconductor integrated ferroelectric memory device is suitable for large scale integration.
The ferroelectric thin layer of the capacitor is required to have much remnant polarization, less dependency to temperature change, and long time retention of its remnant polarization. A conventional titanate zirconate lead (PZT) capacitor has been reported, but is unsuitable for fine pattern lithography, because its main component Pb evaporates and diffuses into the capacitor electrodes at low temperature such as 500.degree. C.
A method of forming the ferroelectric layer by an epitaxial growth method has been reported. The epitaxially grown barium strontium titanate (Ba.sub.x Sr.sub.1-x TiO.sub.3 (BSTO)) ferroelectric layer is formed using RF magnetron sputtering on a strontium ruthenate (SrRuO.sub.3 (SRO)) lower electrode. The SRO electrode is formed on a strontium titanate (SrTiO.sub.3 (STO)) single cryrstal substrate. The magnetron sputter deposited capacitor has preferably has a low rate of miss fit dislocation. BSTO has a larger lattice constant than SRO and the c-axis length of the BLSTO can be artificially controlled by utilizing the epitaxial effect. The c-axis controlled BSTO has a strained lattice structure even when film thickness is 200 nm or more.
The strained lattice structure comprising Ba of over 50 atomic % has been reported to show preferable characteristics such as much remnant polarization at room temperature, long retention of the polarization at around 85.degree. C., and shift of the Curie temperature to higher temperature.
It has been also reported that over 50 atomic % Sr added single crystal BSTO has a dielectric constant of 800, while a polycrystalline layer of same thickness has a dielectric constant of 200. Such a large constant is preferable for a semiconductor memory device, such as a DRAM and Ferroelectric Random Access Memory.
However it is difficult to obtain a 20 mm or more diameter STO substrate with fine crystal structure, and a semiconductor substrate, such as a Si substrate, should be substituted for the STO substrate for practical use, high yield. and low cost.
A practical manufacturing method including the following steps has been also reported, First, a transistor is formed on a Si substrate and an interlayer insulator layer is formed over transistor. Then an opening (contact hole) is formed through the interlayer insulator layer and a single crystal Si plug is formed in the opening by selective vapor phase epitaxial growth or by solid phase epitaxial growth method of an amorphous layer at the bottom c f the opening. An epitaxially grown capacitor is formed on the Si plug to be connected with the transistor electrode and located over the transistor (see U.S. Pat. No. 5,739,563). This method leads to high aspect ratio (depth/width) of the openings, such as 2 or more, and presents difficulty to form numerous openings of such aspect ratio at each of multiple layers. Also it is not preferable to subject the substrate to high temperature above the transistor thermal resistant (around 750-800.degree. C.), while nevertheless such high temperature is desirable to form a fine selectively epitaxially growth layer.
Another practical method utilizing a Semiconductor On Insulator (SOI) substrate is also disclosed in U.S. patent application No. 09/030,809. This second method includes forming an epitaxial capacitor on a main surface of a first substrate and bonding the first substrate and to a second substrate with a SiO.sub.2 layer interposed between the main surface of the first substrate and the surface of the second substrate. Another surface of the second surface is polished and a transistor is formed on the polished surface of the second substrate and connected with the capacitor via a contact plug formed through the SiO.sub.2 layer using a lithography methods A simple method of forming the capacitor and the transistor on different substrate to be overlapped with each other is preferable to obtain higher density integration than the first method.
However in the second method. the contacts through the bonding interface tend to have voids which prohibit perfect electric connection between the transistor and capacitor pair of each memory cell. Also, position alignment of both the capacitor formed on the first substrate and the transistor formed on the second substrate is difficult.